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arch/x86/include/asm/cpufeatures.h

arch/x86/include/asm/cpufeatures.h defines x86 CPU feature bits. 
/*
 * Note: If the comment begins with a quoted string, that string is used
 * in /proc/cpuinfo instead of the macro name.  If the string is "",
 * this feature bit is not displayed in /proc/cpuinfo at all.
 *
 * When adding new features here that depend on other features,
 * please update the table in kernel/cpu/cpuid-deps.c as well.
 */

X86_FEATURE_…

The following defines are all prefixed by X86_FEATURE_.

Intel-defined CPU features, CPUID level 0x00000001 (EDX), word

FPU 0*32+ 0 Onboard FPU
VME 0*32+ 1 Virtual Mode Extensions
DE 0*32+ 2 Debugging Extensions
PSE 0*32+ 3 Page Size Extensions
TSC 0*32+ 4 Time Stamp Counter
MSR 0*32+ 5 Model-Specific Registers
PAE 0*32+ 6 Physical Address Extensions
MCE 0*32+ 7 Machine Check Exception
CX8 0*32+ 8 CMPXCHG8 instruction
APIC 0*32+ 9 Onboard APIC
SEP 0*32+11 SYSENTER/SYSEXIT
MTRR 0*32+12 Memory Type Range Registers
PGE 0*32+13 Page Global Enable
MCA 0*32+14 Machine Check Architecture
CMOV 0*32+15 CMOV instructions (plus FCMOVcc, FCOMI with FPU)
PAT 0*32+16 Page Attribute Table
PSE36 0*32+17 36-bit PSEs
PN 0*32+18 Processor serial number
CLFLUSH 0*32+19 CLFLUSH instruction
DS 0*32+21 "dts" Debug Store
ACPI 0*32+22 ACPI via MSR
MMX 0*32+23 Multimedia Extensions
FXSR 0*32+24 FXSAVE/FXRSTOR, CR4.OSFXSR
XMM 0*32+25 "sse"
XMM2 0*32+26 "sse2"
SELFSNOOP 0*32+27 "ss" CPU self snoop
HT 0*32+28 Hyper-Threading
ACC 0*32+29 "tm" Automatic clock control
IA64 0*32+30 IA-64 processor
PBE 0*32+31 Pending Break Enable

AMD-defined CPU features, CPUID level 0x80000001, word 1

/* Don't duplicate feature flags which are redundant with Intel! */
SYSCALL 1*32+11 SYSCALL/SYSRET
MP 1*32+19 MP Capable
NX 1*32+20 Execute Disable
MMXEXT 1*32+22 AMD MMX extensions
FXSR_OPT 1*32+25 FXSAVE/FXRSTOR optimizations
GBPAGES 1*32+26 "pdpe1gb" GB pages
RDTSCP 1*32+27 RDTSCP
LM 1*32+29 Long Mode (x86-64, 64-bit support)
3DNOWEXT 1*32+30 AMD 3DNow extensions
3DNOW 1*32+31 3DNow

Transmeta-defined CPU features, CPUID level 0x80860001, word 2

RECOVERY 2*32+ 0 CPU in recovery mode
LONGRUN 2*32+ 1 Longrun power control
LRTI 2*32+ 3 LongRun table interface

Other features, Linux-defined mapping, word 3

This range is used for feature bits which conflict or are synthesized
/* FREE, was #define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) "" LFENCE synchronizes RDTSC */
CXMMX 3*32+ 0 Cyrix MMX extensions
K6_MTRR 3*32+ 1 AMD K6 nonstandard MTRRs
CYRIX_ARR 3*32+ 2 Cyrix ARRs (= MTRRs)
CENTAUR_MCR 3*32+ 3 Centaur MCRs (= MTRRs)
K8 3*32+ 4 "" Opteron, Athlon64
ZEN5 3*32+ 5 "" CPU based on Zen5 microarchitecture
P3 3*32+ 6 "" P3
P4 3*32+ 7 "" P4
CONSTANT_TSC 3*32+ 8 TSC ticks at a constant rate
UP 3*32+ 9 SMP kernel running on UP
ART 3*32+10 Always running timer (ART)
ARCH_PERFMON 3*32+11 Intel Architectural PerfMon
PEBS 3*32+12 Precise-Event Based Sampling
BTS 3*32+13 Branch Trace Store
SYSCALL32 3*32+14 "" syscall in IA32 userspace
SYSENTER32 3*32+15 "" sysenter in IA32 userspace
REP_GOOD 3*32+16 REP microcode works well
AMD_LBR_V2 3*32+17 AMD Last Branch Record Extension Version 2
ACC_POWER 3*32+19 AMD Accumulated Power Mechanism
NOPL 3*32+20 The NOPL (0F 1F) instructions
ALWAYS 3*32+21 "" Always-present feature
XTOPOLOGY 3*32+22 CPU topology enum extensions
TSC_RELIABLE 3*32+23 TSC is known to be reliable
NONSTOP_TSC 3*32+24 TSC does not stop in C states
CPUID 3*32+25 CPU has CPUID instruction itself
EXTD_APICID 3*32+26 Extended APICID (8 bits)
AMD_DCM 3*32+27 AMD multi-node processor
APERFMPERF 3*32+28 P-State hardware coordination feedback capability (APERF/MPERF MSRs)
RAPL 3*32+29 AMD/Hygon RAPL interface
NONSTOP_TSC_S3 3*32+30 TSC doesn't stop in S3 state
TSC_KNOWN_FREQ 3*32+31 TSC has known frequency

Intel-defined CPU features, CPUID level 0x00000001 (ECX), word 4

XMM3 4*32+ 0 "pni" SSE-3
PCLMULQDQ 4*32+ 1 PCLMULQDQ instruction
DTES64 4*32+ 2 64-bit Debug Store
MWAIT 4*32+ 3 "monitor" MONITOR/MWAIT support
DSCPL 4*32+ 4 "ds_cpl" CPL-qualified (filtered) Debug Store
VMX 4*32+ 5 Hardware virtualization
SMX 4*32+ 6 Safer Mode eXtensions
EST 4*32+ 7 Enhanced SpeedStep
TM2 4*32+ 8 Thermal Monitor 2
SSSE3 4*32+ 9 Supplemental SSE-3
CID 4*32+10 Context ID
SDBG 4*32+11 Silicon Debug
FMA 4*32+12 Fused multiply-add
CX16 4*32+13 CMPXCHG16B instruction
XTPR 4*32+14 Send Task Priority Messages
PDCM 4*32+15 Perf/Debug Capabilities MSR
PCID 4*32+17 Process Context Identifiers
DCA 4*32+18 Direct Cache Access
XMM4_1 4*32+19 "sse4_1" SSE-4.1
XMM4_2 4*32+20 "sse4_2" SSE-4.2
X2APIC 4*32+21 X2APIC
MOVBE 4*32+22 MOVBE instruction
POPCNT 4*32+23 POPCNT instruction
TSC_DEADLINE_TIMER 4*32+24 TSC deadline timer
AES 4*32+25 AES instructions
XSAVE 4*32+26 XSAVE/XRSTOR/XSETBV/XGETBV instructions
OSXSAVE 4*32+27 "" XSAVE instruction enabled in the OS
AVX 4*32+28 Advanced Vector Extensions
F16C 4*32+29 16-bit FP conversions
RDRAND 4*32+30 RDRAND instruction
HYPERVISOR 4*32+31 Running on a hypervisor

VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5

XSTORE 5*32+ 2 "rng" RNG present (xstore)
XSTORE_EN 5*32+ 3 "rng_en" RNG enabled
XCRYPT 5*32+ 6 "ace" on-CPU crypto (xcrypt)
XCRYPT_EN 5*32+ 7 "ace_en" on-CPU crypto enabled
ACE2 5*32+ 8 Advanced Cryptography Engine v2
ACE2_EN 5*32+ 9 ACE v2 enabled
PHE 5*32+10 PadLock Hash Engine
PHE_EN 5*32+11 PHE enabled
PMM 5*32+12 PadLock Montgomery Multiplier
PMM_EN 5*32+13 PMM enabled

More extended AMD flags: CPUID level 0x80000001, ECX, word 6

LAHF_LM 6*32+ 0 LAHF/SAHF in long mode
CMP_LEGACY 6*32+ 1 If yes HyperThreading not valid
SVM 6*32+ 2 Secure Virtual Machine
EXTAPIC 6*32+ 3 Extended APIC space
CR8_LEGACY 6*32+ 4 CR8 in 32-bit mode
ABM 6*32+ 5 Advanced bit manipulation
SSE4A 6*32+ 6 SSE-4A
MISALIGNSSE 6*32+ 7 Misaligned SSE mode
3DNOWPREFETCH 6*32+ 8 3DNow prefetch instructions
OSVW 6*32+ 9 OS Visible Workaround
IBS 6*32+10 Instruction Based Sampling
XOP 6*32+11 extended AVX instructions
SKINIT 6*32+12 SKINIT/STGI instructions
WDT 6*32+13 Watchdog timer
LWP 6*32+15 Light Weight Profiling
FMA4 6*32+16 4 operands MAC instructions
TCE 6*32+17 Translation Cache Extension
NODEID_MSR 6*32+19 NodeId MSR
TBM 6*32+21 Trailing Bit Manipulations
TOPOEXT 6*32+22 Topology extensions CPUID leafs
PERFCTR_CORE 6*32+23 Core performance counter extensions
PERFCTR_NB 6*32+24 NB performance counter extensions
BPEXT 6*32+26 Data breakpoint extension
PTSC 6*32+27 Performance time-stamp counter
PERFCTR_LLC 6*32+28 Last Level Cache performance counter extensions
MWAITX 6*32+29 MWAIT extension (MONITORX/MWAITX instructions)

Auxiliary flags: Linux defined - For features scattered in various * CPUID levels like 0x6, 0xA etc, word

Reuse free bits when adding new feature flags!
RING3MWAIT 7*32+ 0 Ring 3 MONITOR/MWAIT instructions
CPUID_FAULT 7*32+ 1 Intel CPUID faulting
CPB 7*32+ 2 AMD Core Performance Boost
EPB 7*32+ 3 IA32_ENERGY_PERF_BIAS support
CAT_L3 7*32+ 4 Cache Allocation Technology L3
CAT_L2 7*32+ 5 Cache Allocation Technology L2
CDP_L3 7*32+ 6 Code and Data Prioritization L3
TDX_HOST_PLATFORM 7*32+ 7 Platform supports being a TDX host
HW_PSTATE 7*32+ 8 AMD HW-PState
PROC_FEEDBACK 7*32+ 9 AMD ProcFeedbackInterface
XCOMPACTED 7*32+10 "" Use compacted XSTATE (XSAVES or XSAVEC)
PTI 7*32+11 Kernel Page Table Isolation enabled
KERNEL_IBRS 7*32+12 "" Set/clear IBRS on kernel entry/exit
RSB_VMEXIT 7*32+13 "" Fill RSB on VM-Exit
INTEL_PPIN 7*32+14 Intel Processor Inventory Number
CDP_L2 7*32+15 Code and Data Prioritization L2
MSR_SPEC_CTRL 7*32+16 "" MSR SPEC_CTRL is implemented
SSBD 7*32+17 Speculative Store Bypass Disable
MBA 7*32+18 Memory Bandwidth Allocation
RSB_CTXSW 7*32+19 "" Fill RSB on context switches
PERFMON_V2 7*32+20 AMD Performance Monitoring Version 2
USE_IBPB 7*32+21 "" Indirect Branch Prediction Barrier enabled
USE_IBRS_FW 7*32+22 "" Use IBRS during runtime firmware calls
SPEC_STORE_BYPASS_DISABLE 7*32+23 "" Disable Speculative Store Bypass.
LS_CFG_SSBD 7*32+24 "" AMD SSBD implementation via LS_CFG MSR
IBRS 7*32+25 Indirect Branch Restricted Speculation
IBPB 7*32+26 Indirect Branch Prediction Barrier
STIBP 7*32+27 Single Thread Indirect Branch Predictors
ZEN 7*32+28 "" Generic flag for all Zen and newer
L1TF_PTEINV 7*32+29 "" L1TF workaround PTE inversion
IBRS_ENHANCED 7*32+30 Enhanced IBRS
MSR_IA32_FEAT_CTL 7*32+31 "" MSR IA32_FEAT_CTL configured

Virtualization flags: Linux defined, word 8

TPR_SHADOW 8*32+ 0 Intel TPR Shadow
FLEXPRIORITY 8*32+ 1 Intel FlexPriority
EPT 8*32+ 2 Intel Extended Page Table
VPID 8*32+ 3 Intel Virtual Processor ID
VMMCALL 8*32+15 Prefer VMMCALL to VMCALL
XENPV 8*32+16 "" Xen paravirtual guest
EPT_AD 8*32+17 Intel Extended Page Table access-dirty bit
VMCALL 8*32+18 "" Hypervisor supports the VMCALL instruction
VMW_VMMCALL 8*32+19 "" VMware prefers VMMCALL hypercall instruction
PVUNLOCK 8*32+20 "" PV unlock function
VCPUPREEMPT 8*32+21 "" PV vcpu_is_preempted function
TDX_GUEST 8*32+22 Intel Trust Domain Extensions Guest

Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9

FSGSBASE 9*32+ 0 RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions
TSC_ADJUST 9*32+ 1 TSC adjustment MSR 0x3B
SGX 9*32+ 2 Software Guard Extensions
BMI1 9*32+ 3 1st group bit manipulation extensions
HLE 9*32+ 4 Hardware Lock Elision
AVX2 9*32+ 5 AVX2 instructions
FDP_EXCPTN_ONLY 9*32+ 6 "" FPU data pointer updated only on x87 exceptions
SMEP 9*32+ 7 Supervisor Mode Execution Protection
BMI2 9*32+ 8 2nd group bit manipulation extensions
ERMS 9*32+ 9 Enhanced REP MOVSB/STOSB instructions
INVPCID 9*32+10 Invalidate Processor Context ID
RTM 9*32+11 Restricted Transactional Memory
CQM 9*32+12 Cache QoS Monitoring
ZERO_FCS_FDS 9*32+13 "" Zero out FPU CS and FPU DS
MPX 9*32+14 Memory Protection Extension
RDT_A 9*32+15 Resource Director Technology Allocation
AVX512F 9*32+16 AVX-512 Foundation
AVX512DQ 9*32+17 AVX-512 DQ (Double/Quad granular) Instructions
RDSEED 9*32+18 RDSEED instruction
ADX 9*32+19 ADCX and ADOX instructions
SMAP 9*32+20 Supervisor Mode Access Prevention
AVX512IFMA 9*32+21 AVX-512 Integer Fused Multiply-Add instructions
CLFLUSHOPT 9*32+23 CLFLUSHOPT instruction
CLWB 9*32+24 CLWB instruction
INTEL_PT 9*32+25 Intel Processor Trace
AVX512PF 9*32+26 AVX-512 Prefetch
AVX512ER 9*32+27 AVX-512 Exponential and Reciprocal
AVX512CD 9*32+28 AVX-512 Conflict Detection
SHA_NI 9*32+29 SHA1/SHA256 Instruction Extensions
AVX512BW 9*32+30 AVX-512 BW (Byte/Word granular) Instructions
AVX512VL 9*32+31 AVX-512 VL (128/256 Vector Length) Extensions

Extended state features, CPUID level 0x0000000d:1 (EAX), word

XSAVEOPT 10*32+ 0 XSAVEOPT instruction
XSAVEC 10*32+ 1 XSAVEC instruction
XGETBV1 10*32+ 2 XGETBV with ECX = 1 instruction
XSAVES 10*32+ 3 XSAVES/XRSTORS instructions
XFD 10*32+ 4 "" eXtended Feature Disabling

Extended auxiliary flags: Linux defined - for features scattered in various * CPUID levels like 0xf, e

Reuse free bits when adding new feature flags!
CQM_LLC 11*32+ 0 LLC QoS if 1
CQM_OCCUP_LLC 11*32+ 1 LLC occupancy monitoring
CQM_MBM_TOTAL 11*32+ 2 LLC Total MBM monitoring
CQM_MBM_LOCAL 11*32+ 3 LLC Local MBM monitoring
FENCE_SWAPGS_USER 11*32+ 4 "" LFENCE in user entry SWAPGS path
FENCE_SWAPGS_KERNEL 11*32+ 5 "" LFENCE in kernel entry SWAPGS path
SPLIT_LOCK_DETECT 11*32+ 6 #AC for split lock
PER_THREAD_MBA 11*32+ 7 "" Per-thread Memory Bandwidth Allocation
SGX1 11*32+ 8 "" Basic SGX
SGX2 11*32+ 9 "" SGX Enclave Dynamic Memory Management (EDMM)
ENTRY_IBPB 11*32+10 "" Issue an IBPB on kernel entry
RRSBA_CTRL 11*32+11 "" RET prediction control
RETPOLINE 11*32+12 "" Generic Retpoline mitigation for Spectre variant 2
RETPOLINE_LFENCE 11*32+13 "" Use LFENCE for Spectre variant 2
RETHUNK 11*32+14 "" Use REturn THUNK
UNRET 11*32+15 "" AMD BTB untrain return
USE_IBPB_FW 11*32+16 "" Use IBPB during runtime firmware calls
RSB_VMEXIT_LITE 11*32+17 "" Fill RSB on VM exit when EIBRS is enabled
SGX_EDECCSSA 11*32+18 "" SGX EDECCSSA user leaf function
CALL_DEPTH 11*32+19 "" Call depth tracking for RSB stuffing
MSR_TSX_CTRL 11*32+20 "" MSR IA32_TSX_CTRL (Intel) implemented
SMBA 11*32+21 "" Slow Memory Bandwidth Allocation
BMEC 11*32+22 "" Bandwidth Monitoring Event Configuration
USER_SHSTK 11*32+23 Shadow stack support for user mode applications
SRSO 11*32+24 "" AMD BTB untrain RETs
SRSO_ALIAS 11*32+25 "" AMD BTB untrain RETs through aliasing
IBPB_ON_VMEXIT 11*32+26 "" Issue an IBPB only on VMEXIT
APIC_MSRS_FENCE 11*32+27 "" IA32_TSC_DEADLINE and X2APIC MSRs need fencing
ZEN2 11*32+28 "" CPU based on Zen2 microarchitecture
ZEN3 11*32+29 "" CPU based on Zen3 microarchitecture
ZEN4 11*32+30 "" CPU based on Zen4 microarchitecture
ZEN1 11*32+31 "" CPU based on Zen1 microarchitecture

Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12

AVX_VNNI 12*32+ 4 AVX VNNI instructions
AVX512_BF16 12*32+ 5 AVX512 BFLOAT16 instructions
CMPCCXADD 12*32+ 7 "" CMPccXADD instructions
ARCH_PERFMON_EXT 12*32+ 8 "" Intel Architectural PerfMon Extension
FZRM 12*32+10 "" Fast zero-length REP MOVSB
FSRS 12*32+11 "" Fast short REP STOSB
FSRC 12*32+12 "" Fast short REP {CMPSB,SCASB}
LKGS 12*32+18 "" Load "kernel" (userspace) GS
AMX_FP16 12*32+21 "" AMX fp16 Support
AVX_IFMA 12*32+23 "" Support for VPMADD52[H,L]UQ
LAM 12*32+26 Linear Address Masking

AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13

CLZERO 13*32+ 0 CLZERO instruction
IRPERF 13*32+ 1 Instructions Retired Count
XSAVEERPTR 13*32+ 2 Always save/restore FP error pointers
RDPRU 13*32+ 4 Read processor register at user level
WBNOINVD 13*32+ 9 WBNOINVD instruction
AMD_IBPB 13*32+12 "" Indirect Branch Prediction Barrier
AMD_IBRS 13*32+14 "" Indirect Branch Restricted Speculation
AMD_STIBP 13*32+15 "" Single Thread Indirect Branch Predictors
AMD_STIBP_ALWAYS_ON 13*32+17 "" Single Thread Indirect Branch Predictors always-on preferred
AMD_PPIN 13*32+23 Protected Processor Inventory Number
AMD_SSBD 13*32+24 "" Speculative Store Bypass Disable
VIRT_SSBD 13*32+25 Virtualized Speculative Store Bypass Disable
AMD_SSB_NO 13*32+26 "" Speculative Store Bypass is fixed in hardware.
CPPC 13*32+27 Collaborative Processor Performance Control
AMD_PSFD 13*32+28 "" Predictive Store Forwarding Disable
BTC_NO 13*32+29 "" Not vulnerable to Branch Type Confusion
BRS 13*32+31 Branch Sampling available

Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14

DTHERM 14*32+ 0 Digital Thermal Sensor
IDA 14*32+ 1 Intel Dynamic Acceleration
ARAT 14*32+ 2 Always Running APIC Timer
PLN 14*32+ 4 Intel Power Limit Notification
PTS 14*32+ 6 Intel Package Thermal Status
HWP 14*32+ 7 Intel Hardware P-states
HWP_NOTIFY 14*32+ 8 HWP Notification
HWP_ACT_WINDOW 14*32+ 9 HWP Activity Window
HWP_EPP 14*32+10 HWP Energy Perf. Preference
HWP_PKG_REQ 14*32+11 HWP Package Level Request
HFI 14*32+19 Hardware Feedback Interface

AMD SVM Feature Identification, CPUID level 0x8000000a (EDX), word 15

NPT 15*32+ 0 Nested Page Table support
LBRV 15*32+ 1 LBR Virtualization support
SVML 15*32+ 2 "svm_lock" SVM locking MSR
NRIPS 15*32+ 3 "nrip_save" SVM next_rip save
TSCRATEMSR 15*32+ 4 "tsc_scale" TSC scaling support
VMCBCLEAN 15*32+ 5 "vmcb_clean" VMCB clean bits support
FLUSHBYASID 15*32+ 6 flush-by-ASID support
DECODEASSISTS 15*32+ 7 Decode Assists support
PAUSEFILTER 15*32+10 filtered pause intercept
PFTHRESHOLD 15*32+12 pause filter threshold
AVIC 15*32+13 Virtual Interrupt Controller
V_VMSAVE_VMLOAD 15*32+15 Virtual VMSAVE VMLOAD
VGIF 15*32+16 Virtual GIF
X2AVIC 15*32+18 Virtual x2apic
V_SPEC_CTRL 15*32+20 Virtual SPEC_CTRL
VNMI 15*32+25 Virtual NMI
SVME_ADDR_CHK 15*32+28 "" SVME addr check
/* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */ AVX512VBMI ☰ 16*32+ 1 ☰ AVX512 Vector Bit Manipulation instructions UMIP ☰ 16*32+ 2 ☰ User Mode Instruction Protection PKU ☰ 16*32+ 3 ☰ Protection Keys for Userspace OSPKE ☰ 16*32+ 4 ☰ OS Protection Keys Enable WAITPKG ☰ 16*32+ 5 ☰ UMONITOR/UMWAIT/TPAUSE Instructions AVX512_VBMI2 ☰ 16*32+ 6 ☰ Additional AVX512 Vector Bit Manipulation Instructions SHSTK ☰ 16*32+ 7 ☰ "" Shadow stack GFNI ☰ 16*32+ 8 ☰ Galois Field New Instructions VAES ☰ 16*32+ 9 ☰ Vector AES VPCLMULQDQ ☰ 16*32+10 ☰ Carry-Less Multiplication Double Quadword AVX512_VNNI ☰ 16*32+11 ☰ Vector Neural Network Instructions AVX512_BITALG ☰ 16*32+12 ☰ Support for VPOPCNT[B,W] and VPSHUF-BITQMB instructions TME ☰ 16*32+13 ☰ Intel Total Memory Encryption AVX512_VPOPCNTDQ ☰ 16*32+14 ☰ POPCNT for vectors of DW/QW LA57 ☰ 16*32+16 ☰ 5-level page tables RDPID ☰ 16*32+22 ☰ RDPID instruction BUS_LOCK_DETECT ☰ 16*32+24 ☰ Bus Lock detect CLDEMOTE ☰ 16*32+25 ☰ CLDEMOTE instruction MOVDIRI ☰ 16*32+27 ☰ MOVDIRI instruction MOVDIR64B ☰ 16*32+28 ☰ MOVDIR64B instruction ENQCMD ☰ 16*32+29 ☰ ENQCMD and ENQCMDS instructions SGX_LC ☰ 16*32+30 ☰ Software Guard Extensions Launch Control

AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17

OVERFLOW_RECOV 17*32+ 0 MCA overflow recovery support
SUCCOR 17*32+ 1 Uncorrectable error containment and recovery
SMCA 17*32+ 3 Scalable MCA

Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18

AVX512_4VNNIW 18*32+ 2 AVX-512 Neural Network Instructions
AVX512_4FMAPS 18*32+ 3 AVX-512 Multiply Accumulation Single precision
FSRM 18*32+ 4 Fast Short Rep Mov
AVX512_VP2INTERSECT 18*32+ 8 AVX-512 Intersect for D/Q
SRBDS_CTRL 18*32+ 9 "" SRBDS mitigation MSR available
MD_CLEAR 18*32+10 VERW clears CPU buffers
RTM_ALWAYS_ABORT 18*32+11 "" RTM transaction always aborts
TSX_FORCE_ABORT 18*32+13 "" TSX_FORCE_ABORT
SERIALIZE 18*32+14 SERIALIZE instruction
HYBRID_CPU 18*32+15 "" This part has CPUs of more than one type
TSXLDTRK 18*32+16 TSX Suspend Load Address Tracking
PCONFIG 18*32+18 Intel PCONFIG
ARCH_LBR 18*32+19 Intel ARCH LBR
IBT 18*32+20 Indirect Branch Tracking
AMX_BF16 18*32+22 AMX bf16 Support
AVX512_FP16 18*32+23 AVX512 FP16
AMX_TILE 18*32+24 AMX tile Support
AMX_INT8 18*32+25 AMX int8 Support
SPEC_CTRL 18*32+26 "" Speculation Control (IBRS + IBPB)
INTEL_STIBP 18*32+27 "" Single Thread Indirect Branch Predictors
FLUSH_L1D 18*32+28 Flush L1D cache
ARCH_CAPABILITIES 18*32+29 IA32_ARCH_CAPABILITIES MSR (Intel)
CORE_CAPABILITIES 18*32+30 "" IA32_CORE_CAPABILITIES MSR
SPEC_CTRL_SSBD 18*32+31 "" Speculative Store Bypass Disable

AMD-defined memory encryption features, CPUID level 0x8000001f (EAX), word 19

SME 19*32+ 0 AMD Secure Memory Encryption
SEV 19*32+ 1 AMD Secure Encrypted Virtualization
VM_PAGE_FLUSH 19*32+ 2 "" VM Page Flush MSR is supported
SEV_ES 19*32+ 3 AMD Secure Encrypted Virtualization - Encrypted State
V_TSC_AUX 19*32+ 9 "" Virtual TSC_AUX
SME_COHERENT 19*32+10 "" AMD hardware-enforced cache coherency
DEBUG_SWAP 19*32+14 AMD SEV-ES full debug state swap support

AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20

NO_NESTED_DATA_BP 20*32+ 0 "" No Nested Data Breakpoints
WRMSR_XX_BASE_NS 20*32+ 1 "" WRMSR to {FS,GS,KERNEL_GS}_BASE is non-serializing
LFENCE_RDTSC 20*32+ 2 "" LFENCE always serializing / synchronizes RDTSC
NULL_SEL_CLR_BASE 20*32+ 6 "" Null Selector Clears Base
AUTOIBRS 20*32+ 8 "" Automatic IBRS
NO_SMM_CTL_MSR 20*32+ 9 "" SMM_CTL MSR is not present
SBPB 20*32+27 "" Selective Branch Prediction Barrier
IBPB_BRTYPE 20*32+28 "" MSR_PRED_CMD[IBPB] flushes all branch type predictions
SRSO_NO 20*32+29 "" CPU is not affected by SRSO

X86_BUG_

The following defines are all prefixed by X86_BUG_. 
#define X86_BUG(x)			(NCAPINTS*32 + (x))
F00F 0 Intel F00F
FDIV 1 FPU FDIV
COMA 2 Cyrix 6x86 coma
AMD_TLB_MMATCH 3 "tlb_mmatch" AMD Erratum 383
AMD_APIC_C1E 4 "apic_c1e" AMD Erratum 400
11AP 5 Bad local APIC aka 11AP
FXSAVE_LEAK 6 FXSAVE leaks FOP/FIP/FOP
CLFLUSH_MONITOR 7 AAI65, CLFLUSH required before MONITOR
SYSRET_SS_ATTRS 8 SYSRET doesn't fix up SS attrs
ESPFIX 9 "" IRET to 16-bit SS corrupts ESP/RSP high bits (Only defined if also CONFIG_X86_32 is defined (64-bit kernels do't use X86_BUG_ESPFIX)
NULL_SEG 10 Nulling a selector preserves the base
SWAPGS_FENCE 11 SWAPGS without input dep on GS
MONITOR 12 IPI required to wake up remote CPU
AMD_E400 13 CPU is among the affected by Erratum 400
CPU_MELTDOWN 14 CPU is affected by meltdown attack and needs kernel page table isolation
SPECTRE_V1 15 CPU is affected by Spectre variant 1 attack with conditional branches
SPECTRE_V2 16 CPU is affected by Spectre variant 2 attack with indirect branches
SPEC_STORE_BYPASS 17 CPU is affected by speculative store bypass attack
L1TF 18 CPU is affected by L1 Terminal Fault
MDS 19 CPU is affected by Microarchitectural data sampling
MSBDS_ONLY 20 CPU is only affected by the MSDBS variant of BUG_MDS
SWAPGS 21 CPU is affected by speculation through SWAPGS
TAA 22 CPU is affected by TSX Async Abort(TAA)
ITLB_MULTIHIT 23 CPU may incur MCE during certain page attribute changes
SRBDS 24 CPU may leak RNG bits if not mitigated
MMIO_STALE_DATA 25 CPU is affected by Processor MMIO Stale Data vulnerabilities
MMIO_UNKNOWN 26 CPU is too old and its MMIO Stale Data status is unknown
RETBLEED 27 CPU is affected by RETBleed
EIBRS_PBRSB 28 EIBRS is vulnerable to Post Barrier RSB Predictions
SMT_RSB 29 CPU is vulnerable to Cross-Thread Return Address Predictions
GDS 30 CPU is affected by Gather Data Sampling
TDX_PW_MCE 31 CPU may incur #MC if non-TD software does partial write to TDX private memory
SRSO 1*32 + 0 AMD SRSO bug
DIV0 1*32 + 1 AMD DIV0 speculation bug

See also

arch/x86/kernel/cpu/cpuid-deps.c (which declares dependencies between CPUIDs).
arch/x86/kernel/cpu/capflags.c
arch/x86/boot/cpustr.h
/proc/cpuinfo

Links

Source code in github

Index